Novel Hafnium-Based Compound Metal Oxide Gate Dielectrics for Advanced CMOS Technology

Comparative Study on the Impact of TiN and Mo Metal Gates on MOCVD-Grown HfO2 and ZrO2 High-κ Dielectrics for CMOS Technology

The reduction of the equivalent oxide thickness (EOT) of the gate oxide has emerged as one of the most difficult tasks addressing future CMOS technology. In order to overcome gate tunneling, the introduction of so-called high-κ materials will be necessary [1]. Hafnium dioxide, HfO2 [2], zirconium dioxide, ZrO2 [3], and their silicates are assumed to be the most promising candidates to fulfil th...

Electrical and Material Characteristics of Hafnium-based Multi-metal High-k Gate Dielectrics for Future Scaled CMOS Technology: Physics, Reliability, and Process Development

Process Optimization and Integration of Hfo2 and Hf-silicates

We have established in-line characterization techniques for analyzing the bulk and interface-charge properties of dielectric films, for process optimization. Surface charge analysis (SCA) is used to determine the densities of interface states, fixed charge, and near-interface traps in ultra-thin dielectrics, and is useful for tracking the influence of post-deposition processing on interface-cha...

Capacitance-voltage studies of atomic-layer-deposited MOS structrures on Gallium Arsenide and other III-V compound semiconductors Master of Science in Electrical and Computer Engineering P. Ye, Chair

Yang, Tian M.S.E.C.E, Purdue University, December, 2007. Capacitance-voltage studies of atomic-layer-deposited MOS structrures on Gallium Arsenide and other III-V compound semiconductors . Major Professor: Peide Ye. Si-based CMOS devices with traditional structure are approaching the fundamental physical limits. New device structures and materials must be explored to continue the trend of incre...

Reaction/annealing pathways for forming ultrathin silicon nitride films for composite oxide–nitride gate dielectrics with nitrided crystalline silicon–dielectric interfaces for application in advanced complementary metal–oxide–semiconductor devices

Aggressive scaling of complementary metal–oxide–semiconductor ~CMOS! devices requires gate dielectrics with an oxide equivalent thickness, tox,eq;1 nm or less by the product introduction year 2012. Direct tunneling presents a significant performance limitation in field-effect transistors ~FETs! with homogeneous oxide gate dielectrics ,1.7 nm. Boron diffusion from p poly-Si gate electrodes in p-...